The present invention relates to the field of monitoring the operation of input devices. More particularly, the invention relates to an apparatus and a method for providing a fast, low power consumption, detection of at least one depressed key in a resistive matrix keyboard.
Keyboards are widespread as a standard input device for many electronic devices. In Personal Computers (PC), for instance, the keyboard is the main input device available for users to enter data and interact with the PC.
PC keyboards usually comprise keys for typing, numbers, alphabetic letters, algebraic operators, special functions and more. Because of the large number of keys, it is customary to arrange the keys in a matrix, each key being implemented by a switch that has a unique two-dimensional location of the matrix, indicated by a row and column number. When a key is pressed, the mechanical operation is transferred to a corresponding switch, which in response changes its state to a conducting state. In order to detected depressed keys, the matrix is scanned to reveal switches that are closed (conducting), corresponding to a pressed key. A typical conventional keyboard further comprises an encoder, which translates the location (row and column) of the closed switch in the matrix into a code symbol that is later used to uniquely identify the depressed key.
FIG. 1 schematically illustrates a prior art keyboard matrix depicting the matrix scan procedure that is required to detect a depressed key. The matrix is constructed from horizontal and vertical conducting lines, which form the matrix rows and columns, respectively. Two columns (KBSout1, KBSout2) are the matrix""s drive lines, and two rows (KBSin1, KBSin2) represent the sense lines of the keyboard matrix. KBSout1, and KBSout2 are grounded through the N-channel MOSFET transistors, Q1 and Q2, respectively. Each transistor implements an Electronic Switch (ES), which is activated when a Scan Pulse (SP) is applied to its gate.
The rows and columns junctions of the keyboard matrix in FIG. 1 are coupled by the Key Switches (KS): KS11, KS12, KS21, and KS22. The matrix is scanned column by column by applying an SP to each drive line ES, one at a time. When an SP is applied to one of the drive lines ES (e.g., ES1), the corresponding electric switch that is connected to that drive line is turned ON (i.e., Q1 is switching to its conducting state), thereby enabling electric current flow through that drive line to ground. If all the KSs are open, then no current flows and the voltage level of all the sense lines equals VCC (normally a xe2x80x9c1xe2x80x9d logic). If a KSji on the scanned drive line is closed (i.e., a pressed key), when ESi is applied with a Scan Pulse (SP) KBSouti is pulled to LOW. Consequently, the electric voltage on the KBSin line that corresponds to the row that contains the closed switch (KBSinj) drops to a lower level voltage Vd, thereby indicating the row number (i.e., j) and the column number (i.e., i) of the closed switch.
The value of the resistors Rp and the transistors"" on voltage (Vd) are designed such that the row voltage Vj (vj=Vd, j=1, 2) is identified as a xe2x80x9c0xe2x80x9d logic by the input gate on KBSinj. This way, the depressed keys"" rows and columns are located. For example, if an SP is applied to drive line KBSout1 (i.e., to ES1), and KS11 is closed, the voltage on sense line KBSin1 drops from VCC to Vd, indicating a key closure between the KBSout1 column and the KBSin1 row.
False detection occurs when several keys are simultaneously pressed. This is known in the art as the xe2x80x9cphantom keyxe2x80x9d problem, that is, when closed circuits are formed by several KS being pressed simultaneously, which results in false indication of pressed keys. For example, if KS11, KS12, and KS22 of the keyboard matrix are simultaneously pressed when the SP is applied to KBSout1 (ES1), the current that flows through Rp2, KS22, KS12 (in the reverse direction) and KS11 to ground, causes a voltage drop (from VCC to Vd) on KBSin2, resulting in false indication of KS21 as closed.
Solving the xe2x80x9cphantom keyxe2x80x9d problem is necessary to achieve a proper detection whenever several keys are simultaneously pressed. This problem is also known as xe2x80x9cn key rollover.xe2x80x9d The keyboard encoder is designed to resolve xe2x80x9cn key rolloverxe2x80x9d conditions and xe2x80x9cphantomxe2x80x9d keys, and in addition, to perform switch contact debouncing.
A prior art implementation that resolves xe2x80x9cphantomxe2x80x9d key problems is depicted in FIG. 2, which illustrates a keyboard construction with diodes connected in series to each KS of the keyboard matrix. The diodes in this implementation eliminate the xe2x80x9creversexe2x80x9d current flow through KS12 (with reference to the previous example) and therefore prevent the xe2x80x9cphantom keyxe2x80x9d problem. In this way, xe2x80x9cn key rolloverxe2x80x9d is prevented. This solution does have the side effect that the diodes forward drop adds to Vd, which forces a higher value for the highest voltage that is still considered as a xe2x80x9c0xe2x80x9d logic state of the KBSin inputs. In addition, keyboard parts count is substantially increased (series diodes) resulting in an expensive assembly of the keyboard.
Another keyboard implementation that resolves the xe2x80x9cn key rolloverxe2x80x9d problem is the resistive matrix keyboard, depicted in FIG. 3, in which a closed KS presents a non-zero resistance rather than a short circuit. When a key is pressed, its resistance provides the electrical connection required for indicating a key closure. The resistive matrix outputs a set of analog signals, rather than digital logic values. An array of comparators (CMP), each of which is fed by a predetermined threshold voltage, is used to distinguish between the voltage levels cause by one, or xe2x80x9cn keyxe2x80x9d pressing.
A diversity of analog voltage levels appears at the resistive matrix rows KBSinj, in accordance to the number of keys pressed. The voltage difference between an actual (real) KS closure and a faulty closure indication (i.e., xe2x80x9cphantomxe2x80x9d key) is relatively small, so that the threshold voltage level (Vref) should be carefully determined to ensure a correct detection of the pressed keys by the set of comparators. However, deviations of the KS resistance values in the matrix result in changes of the voltage levels, which may be a source for faulty KS closure detection. The voltage level variation is affected by tolerances of the KS resistance values during production and by environmental effects like temperature, moisture, dust and corrosion of the contacts. Moreover, the threshold voltage levels usually fluctuate over time and temperature, contributing more imprecision.
In the design and manufacture of a portable PC (e.g., a xe2x80x9claptopxe2x80x9d), a great effort is invested to substantially reduce the device""s size, weight, and power consumption. Reduction of the power consumption is essential to achieve a long term operation of electronic mobile and wireless devices operating from a battery power supply. In order to reduce the device""s size, and increase the efficiency, an embedded controller (EC) is utilized to interact with the laptop""s input/output (I/O) devices.
The power consumption of the EC is influenced by the controller operation. It is desired to reduce the controller activity to a minimum by executing a fast matrix scan and by halting the controller operation when it is not needed. When halted, the system can be in a standby mode, in which the matrix is only sensed to detect a press condition on any of the keys, or on a specific subset of them, as an indication for activity. This is known as xe2x80x9cany key pressedxe2x80x9d detection, and it is performed by applying one SP to all the drive lines and testing the sense lines voltage levels. If a key is pressed it is detected by a logic xe2x80x9c0xe2x80x9d in one of the KBSin inputs, this indication is utilized as a wake event to the EC. In response, once the activity in the EC is resumed, it will use the normal key scan process to detect exactly which key is pressed.
The Mitsubishi 3886 device is a prior art micro-computer with an embedded comparator circuit, which is utilized to interface with a resistive matrix. The comparator circuit compares simultaneously up to eight (8) analog inputs with a single reference voltage. An internal resistive voltage divider is utilized to produce the reference voltage. Only one division ratio is provided or the use of an external voltage reference is required, with the increased cost associated. The comparator circuit is operated by software, and thus, the microcomputer is always involved in monitoring the keyboard. Any key detection is possible, only when the processor is active since no wakeup interrupt is available from the comparator. Also, processor activity is required fro controlling the current consumption of the circuit via timed enable and disable. No hardware support is provided for debouncing the comparator output against noise, or for controlling the thresholds in case of misfit.
Other prior art methods utilize Analog to Digital (A/D) converters to monitor and detect the resistive matrix sense line signals (KBSin). A/D conversion of the matrix analog signals enables digital processing with higher accuracy, and overcomes the resistive matrix imprecision that was previously discussed. The Hitachi H8S/2144 and B8S/2148 series are prior art single-chip microcomputers with an embedded A/D converter. A/D conversion of the sense line signals is selected through an analog multiplexer. A successive approximation A/D is utilized to measure the input voltage of one input at a time. A complete scan of the matrix sense lines involves a sequence of conversions. For a complete scan of the matrix n times m conversions are required, where n is the number of rows and m is the number of columns. This substantially increases the current consumption required for the conversion due to the large number of conversion operations and the continuous intervention of the processor. In addition, this scheme does not allow xe2x80x9cany key press detectionxe2x80x9d since the KBSin signals need to be scanned.
All the methods described above have not yet provided satisfactory solutions for fast xe2x80x9cn key rolloverxe2x80x9d with low power consumption implementations for resistive matrix keyboards.
It is an object of the present invention to provide an apparatus and a method for low power xe2x80x9cany key pressedxe2x80x9d detection for a resistive keyboard matrix that does not require software activity in the controller.
It is another object of the present invention to provide an apparatus and method for fast detection of actual key depression in a resistive keyboard matrix, with improved tolerance to resistive values variations and system noise rejection through debouncing.
It is still another object of the present invention to overcome voltage deviations caused by tolerances of pull-up resistors, being part of a monolithic control circuit of a resistive matrix.
Other objects and advantages of the invention will become apparent as the description proceeds.
The present invention is directed to a method for providing a fast, low power consumption, detection of at least one depressed key in a resistive matrix keyboard. The common contact of each row of a resistive matrix is connected to a first input of each of a plurality of analog/digital comparators capable of switching between high and low voltage states. A common predetermined reference voltage applied to a second input of each analog/digital comparator is generated by using a digital to analog converter. The output of each of the analog/digital comparators is in a first state if the voltage level applied to the first input is higher than the reference voltage, and in a second state if the voltage level applied to the first input of the analog/digital comparator is lower than the reference voltage. The contacts of all columns of the resistive matrix are simultaneously connected to a voltage level that enables current to flow through the resistors that are connected to each column, and changes in the output state of one or more analog/digital comparators are sought. The generation of the reference voltage and the connection of columns are periodically repeated if no change is detected. Upon detecting a change of state of at least one analog/digital comparator, the reference voltage is varied in an up-going or in a down-going direction by using the digital to analog converter, so that the varied reference voltage is equal to the voltage that is applied to the first input of each analog/digital comparator, at least once. Whenever the varied reference voltage reaches the voltage that is applied to the first input of an analog/digital comparator, a change of state in that analog/digital comparator is detected, and the digital word of the digital to analog converter that corresponds to the value of the reference voltage reached that caused the change of state in that analog/digital comparator is obtained. The digital word obtained for each analog/digital comparator may be stored in a memory. Preferably, changes in the output state of one or more analog/digital comparators are sought at the lowest frequency that is sufficient to detect all key press and release events.
Preferably, a signal indicating a change of state of at least one analog/digital comparator or the absence of such a change of state is output into a control circuit. The frequency of seeking changes in the output state of at least one analog/digital comparator is controlled by the control circuit, to be lower if no change in the output state of at least one analog/digital comparator is obtained. The frequency of varying the reference voltage is controlled by the control circuit, to be higher in response to a change in the output state of at least one analog/digital comparator.
Preferably, the value of the common reference voltage is determined by the following steps:
(a) defining a first range of voltages expected to be at an input of each analog/digital comparator, the first range of voltages corresponding to a voltage that results from an actual depression of a key in a row;
(b) defining a second range of voltages expected to be at am input of each analog/digital comparator, the second range of voltages being spaced from the first range of voltages, and corresponding to voltages that result from: no actual depression of a key, or from a false depression of a key, or from multiple depression of keys in a row; and
(c) determining a value of the common reference voltage to be between the first range of voltages and the second range of voltages.
The circuitry for detecting a change of state combines all outputs of the plurality of comparators, so as to allow the simultaneous detection of a change of state without periodically scanning the columns of the resistive matrix.
The present invention is also directed to an apparatus for providing a fast, low power consumption detection of at least one depressed key in a resistive matrix keyboard, where the apparatus comprises:
(a) a plurality of analog/digital comparators, each analog/digital comparator of which having a first input connected to a common contact of a different row of a resistive matrix and capable of switching between high and low voltage states;
(b) a digital to analog converter, connected to a second input of each of said plurality of analog/digital comparators, for generating a common predetermined reference voltage and for applying the common predetermined reference voltage to the second input of each of the plurality of analog/digital comparators, wherein the output of each of the plurality of analog/digital comparators is in a first state if a voltage level applied to the first input of an analog/digital comparator is higher than the reference voltage, and in a second state if the voltage level applied to the first input of the analog/digital comparator, is lower than the reference voltage;
(c) circuitry for detecting a change of state in at least one analog/digital comparator;
(d) a control circuit for controlling a frequency of detection of a change of state and for varying the reference voltage in an up-going or a down-going direction by inputting different digital words to the digital to analog converter at a desired rate; and
(e) a data bus for outputting the digital words of the digital to analog converter that correspond to the values of the reference voltage that cause a change of state in each of said plurality of analog/digital comparators.
Preferably, the apparatus may further comprise at least one memory for storing digital words of the digital to analog converter upon receiving corresponding control commands from the control circuit and a data bus for outputting the digital words stored in at least one memory. An AND/NAND gate may be used for detecting a change of state in one or more analog/digital comparators, each input of the AND/NAND gate being connected to the output of a different analog/digital comparator. The circuitry for detecting a change of state may combine all outputs of the plurality of analog/digital comparators, to allow the simultaneous detection of a change of state without periodically scanning columns of the resistive matrix.
The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the Detailed Description of the Invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject matter of the claims of the invention. Those skilled in the art should appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
Before undertaking the Detailed Description of the Invention, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: The terms xe2x80x9cincludexe2x80x9d and xe2x80x9ccomprisexe2x80x9d and derivatives thereof, mean inclusion without limitation, the term xe2x80x9corxe2x80x9d is inclusive, meaning xe2x80x9cand/orxe2x80x9d; the phrases xe2x80x9cassociated withxe2x80x9d and xe2x80x9cassociated therewith,xe2x80x9d as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, to bound to or with, have, have a property of, or the like; and the term xe2x80x9ccontroller,xe2x80x9d xe2x80x9cprocessor,xe2x80x9d or xe2x80x9capparatusxe2x80x9d means any device, system or part thereof that controls at least one operation. Such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document. Those of ordinary skill should understand that in many instances (if not in most instances), such definitions apply to prior, as well as future uses of such defined words and phrases.